Search - nios timer

[Other resource] timeforsopcbuider

Description: NIOS II IDE 编程，定时器测试程序，仅供参考。-NIOS II IDE programming timer testing procedures, for information purposes only.
Platform: | Size: 6278 | Author: 张建 | Hits:

[VHDL-FPGA-Verilog] timeforsopcbuider

Description: NIOS II IDE 编程，定时器测试程序，仅供参考。-NIOS II IDE programming timer testing procedures, for information purposes only.
Platform: | Size: 399360 | Author: 张建 | Hits:

[Other Embeded program] NiosII_software_tutorial

Description: NiosII的软件开发手册，包括了niosII IDE开发环境的介绍，HAL系统库的介绍以及使用HAL进行程序开发-NiosII software development manuals, including the development environment IDE niosII presentation HAL system for the introduction and use of the procedures for the development of HAL
Platform: | Size: 776192 | Author: 林德 | Hits:

[Embeded-SCM Develop] ADDAButtonLED

Description: 此源码是利用altera公司的nios II IDE开发的源码，功能是在开发板上实现键盘控制的AD/DA发送接受正弦波、4×4小键盘按键通过串口显示、定时器控制led灯循环点亮的功能。-This source is the use of altera company nios II IDE to develop the source, function is to achieve in the development of on-board keyboard control AD/DA to send accept sine, 4 × 4 keypad buttons show through the serial port, timer control led lights Highlight the function of the cycle.
Platform: | Size: 159744 | Author: zeng xuan | Hits:

[Embeded-SCM Develop] time

Description: altera 中基于NIOS软核系统的定时器应用程序 -altera-based NIOS soft-core system timer application
Platform: | Size: 406528 | Author: 黄杰 | Hits:

[Embeded-SCM Develop] timer0

Description: NIOS系统中的定时器编程实现，使用C语言实现NIOS系统中定时器的编程，结合实验板上的led，七段数码管，实现计时器的功能-NIOS system timer programming, using C language NIOS system timer programming, combined with the experimental panel led, Seven-Segment LED to achieve the functions of the timer
Platform: | Size: 3072 | Author: 林华 | Hits:

[Embeded-SCM Develop] nios_example

Description: nios范例（含源代码），包含dma控制器，io中断，串口中断，定时器中断-nios sample (including source code), including dma controller, io interrupt, serial port interrupt, timer interrupt
Platform: | Size: 204800 | Author: 李扬 | Hits:

[VHDL-FPGA-Verilog] nios

Description: altera ep2c8V2 开发实例 timer uart I2C key interrupt 等-altera ep2c8V2 examples timer uart I2C key interrupt etc.
Platform: | Size: 11765760 | Author: chris | Hits:

[VHDL-FPGA-Verilog] Lab2b

Description: A C example for Nios II to use the timer and to obtain the time execution performance
Platform: | Size: 1024 | Author: gios78 | Hits:

[VHDL-FPGA-Verilog] nios-II

Description: 很好地描述了NOISII的串口、定时中断等各种实例-A good description of the NOISII the serial port, timer interrupt, and other examples of
Platform: | Size: 204800 | Author: 李大伟 | Hits:

[ARM-PowerPC-ColdFire-MIPS] tst_it

Description: Altera 测试 Interval Timer 的源码在NIOS IDE下调试通过-Altera Test Interval Timer source code to debug through the NIOS IDE
Platform: | Size: 372736 | Author: liuzhenyu | Hits:

[VHDL-FPGA-Verilog] timer

Description: nios ii中时钟的测试程序。。求成全-something about timer
Platform: | Size: 11670528 | Author: hq | Hits:

[VHDL-FPGA-Verilog] timer

Description: 在nios环境下，结合verilog语言开发，功能是结合系统定时器的流水灯操作-Nios environment, combined with the verilog language development is a combination of water of the system timer lamp operating
Platform: | Size: 17015808 | Author: zq | Hits:

[VHDL-FPGA-Verilog] nios-II

Description: NiosII范例，包括了DMA控制，串口通信，定时器中断，以及NIOS的部分范例，对于FPGA内核的开发很有帮助。-NiosII example, including the DMA control, serial communication, timer interrupt, as well as some examples of NIOS, development will be helpful for the FPGA core.
Platform: | Size: 204800 | Author: 张奎 | Hits:

[ARM-PowerPC-ColdFire-MIPS] timer

Description: 基于FPGA nios II 的软核处理器定时器的应用程序-Based on FPGA nios II soft-core processor timer application
Platform: | Size: 1024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] timer

Description: 在NIOS IDE开发环境下实现对定时器的编程，适合新手入门使用-In NIOS IDE development environment to achieve the timer programming, suitable for beginners to use
Platform: | Size: 1077248 | Author: 宋子健 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 本代码用verilog语言描述，在nios上操作，实现了定时器的设置和中断操作，并结合timestamp读取程序运行的时间。-The code to use verilog language to describe, in nios on operation, to achieve the timer settings and interrupt operation, combined with the timestamp reads the program run.
Platform: | Size: 19273728 | Author: 普尔 | Hits:

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[Other resource] timeforsopcbuider

[VHDL-FPGA-Verilog] timeforsopcbuider

[Other Embeded program] NiosII_software_tutorial

[Embeded-SCM Develop] ADDAButtonLED

[Embeded-SCM Develop] time

[Embeded-SCM Develop] timer0

[Embeded-SCM Develop] nios_example

[VHDL-FPGA-Verilog] nios

[VHDL-FPGA-Verilog] Lab2b

[VHDL-FPGA-Verilog] nios-II

[ARM-PowerPC-ColdFire-MIPS] tst_it

[VHDL-FPGA-Verilog] timer

[VHDL-FPGA-Verilog] timer

[VHDL-FPGA-Verilog] nios-II

[ARM-PowerPC-ColdFire-MIPS] timer

[VHDL-FPGA-Verilog] timer

[VHDL-FPGA-Verilog] timer

[VHDL-FPGA-Verilog] led

[Software Engineering] NIOS_TIMER

[VHDL-FPGA-Verilog] 9_timer

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